The present invention relates generally to electrostatic discharge (ESD) protection and, more particularly, to circuits for providing ESD protection in a multi-power domain.
A semiconductor integrated circuit (IC) is generally susceptible to electrostatic discharge (ESD), which may damage or destroy the IC. ESD generally refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a relatively large amount of current passes through a part of the IC. The current surge may exceed what the IC can normally tolerate and may cause undesirable impact to the IC's operation or damage the IC or its components. To prevent ESD damages, many ICs have ESD protection circuit or circuits and may rely on different approaches of ESD protection for different applications.
In a large electronic system having multiple sub-systems, such as in a computer system, there are generally a number of power supplies providing different power levels. The sub-systems, such as ICs and chips in the system, often require separate power supplies with different voltages. And interface circuits may exist to provide communications of signals between two sub-systems. However, interface circuits between the sub-systems, if not properly protected, are susceptible to damages by ESD. FIG. 1 is an exemplary circuit diagram of a conventional multi-power system 10 with interface circuits. Referring to FIG. 1 as an example, the system 10 includes rail-to-rail ESD clamp circuits 11 and 12 for ESD protection. However, when ESD occurs, because power supplies in the system 10 remain floating, a p-type metal-oxide-semiconductor (“PMOS”) transistor Mp is turned on and supplies an ESD current IESD toward an n-type metal-oxide-semiconductor (“NMOS”) transistor Mn of an interface device 15. The ESD current may damage or degrade the gate oxide of the NMOS transistor Mn. According to the example, ESD can easily occur in a system having multiple power supplies, and it may be desirable to provide ESD protection circuits to protect interface circuits from being damaged by ESD. Furthermore, it is necessary that the ESD clamp circuits meet the requirements of different power voltages.